`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:00:26 04/20/2011 
// Design Name: 
// Module Name:    WriteBack 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module WriteBack(MemtoReg, memData, ALUresult, writeDstIn, RegWriteIn, writeDstOut,
	RegWriteOut, writeData);

	input MemtoReg;
	input [15:0] memData;
	input [15:0] ALUresult;
	input [3:0] writeDstIn;
	input RegWriteIn;
	
	//Just passing through
	output [3:0] writeDstOut;
	output RegWriteOut;
	output [15:0] writeData;
	
	//Buffers added to safeguard against hold violations
	delay_buffer_4bit i_buf1(.a(writeDstIn), .y(writeDstOut));
	delay_buffer_1bit i_buf2(.a(RegWriteIn), .y(RegWriteOut));

	Mux_2to1_16bits i_Mux1(
	.a(ALUresult),
	.b(memData),
	.sel(MemtoReg),
	.out(writeData));

endmodule
